1 ? 3mhz, bimos micropro cessor operational amplifiers with mosfet input/cmos output the CA5260A and ca507.260 ar e integrated-circuit operational amplifiers that combine the advantage of both cmos and bipolar transistors on a monolithic chip. the ca5260 series circuits are dual versions of the popular ca5160 series. they are designed and guaranteed to operate in microprocessor or logic systems that use +5v supplies. gate-protected p-channel mosf et (pmos) transistors are used in the input circuit to pr ovide very-high-input impedance, very-low-input current, and ex ceptional speed performance. the use of pmos field-effect transistors in the input stage results in common-mode input-voltage capability down to 0.5v below the negative-supply terminal , an important attribute in single-supply applications. a complementary-symmetry mo s (cmos) transistor-pair, capable of swinging the output voltage to within 10mv of either supply-voltage terminal (at very high values of load impedance), is employed as the output circuit. the ca5260 series circuits operate at supply voltages ranging from 4.5v to 16v, or 2.25v to 8v when using split supplie s. the ca5260, CA5260A have guaranteed specifications for 5v operation over the fu ll military temper ature range of -55 o c to 125 o c . features ? mosfet input stage provides - very high z i = 1.5t ? (1.5 x 10 12 ? ) (typ) - very low i i = 5pa (typ) at 15v operation = 2pa (typ) at 5v operation ? ideal for single supply applications ? common mode input voltage range includes negative supply rail; input terminals can be swung 0.5v below negative supply rail ? cmos output stage permits signal swing to either (or both) supply rails ? CA5260A, ca5260 have full military temperature range guaranteed specifications for v+ = 5v ? CA5260A, ca5260 are guaranteed to operate down to 4.5v for a ol ? fully guaranteed to operate from -55 o c to 125 o c at v+ = 5v, v- = gnd applications ? ground referenced single supply amplifiers ? fast sample-hold amplifiers ? long duration timers/monostables ? ideal interface with digital cmos ? high input impedance wideband amplifiers ? voltage followers (e.g., follower for single supply d/a converter) ? voltage regulators (permits control of output voltage down to 0v) ? wien bridge oscillators ? voltage controlled oscillators ? photo diode sensor amplifiers ? 5v logic systems ? microprocessor interface pinout ca5260 (pdip, soic) top view ordering information part number (brand) temp. range ( o c) package pkg. dwg. # CA5260Am96 (5260a) -55 to 125 8 ld soic tape and reel m8.15 ca5260e -55 to 125 8 ld pdip e8.3 ca5260m (5260) -55 to 125 8 ld soic m8.15 ca5260m96 (5260) -55 to 125 8 ld soic tape and reel m8.15 n on inv. input (a) v- 1 2 3 8 7 6 5 v+ output (b) inv. input (b) non inv. input (b) output (a) a 4 b + - + - inv. input (a) fn1929.4 ca5260, CA5260A data sheet august 2003 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 absolute m aximum ratings thermal information supply voltage (between v+ and v- terminals) . . . . . . . . . . . . 16v differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8v input voltage . . . . . . . . . . . . . . . . . . . . . . . . (v+ +8v) to (v- -0.5v) input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1ma output short circuit duration (note 1). . . . . . . . . . . . . . . . indefinite operating conditions temperature range. . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c thermal resistance (typical, note 2) ja ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 soic package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 maximum junction temperature (die) . . . . . . . . . . . . . . . . . . . 175 o c maximum junction temperature (plastic package) . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. short circuit may be applied to ground or to either supply. 2. ja is measured with the component mount ed on an evaluation pc board in free air. electrical specifications typical values intended only for design guidance, v+ = 5v, v- = 0v, t a = 25 c, unless otherwise specified parameter symbol test conditions typical values units ca5260 CA5260A input resistance r i 1.5 1.5 t ? input capacitance c i f = 1mhz 4.3 4.3 pf unity gain crossover frequency f t 3 3 mhz slew rate sr v out = 2.5v p-p 5 5 v/ s transient response c l = 25pf, r l = 2k ? (voltage follower) rise time t r 0.09 0.09 s overshoot os 10 10 % settling time (to <0.1%, v in = 4v p-p ) t s c l = 25pf, r l = 2k ? (voltage follower) 1.8 1.8 s electrical specifications t a = 25 o c, v+ = 5v, v- = 0v parameter symbol test conditions ca5260 CA5260A units min typ max min typ max input offset voltage v io v o = 2.5v - 2 15 - 1.5 4 mv input offset current i io v o = 2.5v - 1 10 - 1 10 pa input current i i v o = 2.5v - 2 15 - 2 15 pa common mode rejection ratio cmrr v cm = 0 to 1v 70 85 - 80 85 - db v cm = 0 to 2.5v 50 55 - 50 55 - db common mode input voltage range v lcr + 2.5 3 - 2.5 3 - v v lcr - - -0.5 0 - -0.5 0 v power supply rejection ratio psrr ? v+ = 1v; ? v- = 1v 70 84 - 75 84 - db large signal voltage gain (note 3) a ol r l = , v o = 0.5 to 4v 105 111 - 107 113 - db r l = 10k ? , v o = 0.5 to 3.6v 80 86 - 83 86 - db source current i source v o = 0v 1.75 2.2 - 1.75 2.2 - ma sink current i sink v o = 5v 1.70 2 - 1.70 2 - ma output voltage v om + r l = 4.99 5 - 4.99 5 - v v om - - 0 0.01 - 0 0.01 v ca5260, CA5260A ca5260, CA5260A
3 v om + r l = 10k ? 4.4 4.7 - 4.4 4.7 - v v om - - 0 0.01 - 0 0.01 v v om + r l = 2k ? 3 3.4 - 3 3.4 - v v om - - 0 0.01 - 0 0.01 v supply current i supply v o = 0v - 1.60 2.0 - 1.60 2.0 ma v o = 2.5v - 1.80 2.25 - 1.80 2.25 ma note: 3. for v+ = 4.5v and v- = gnd; v out = 0.5v to 3.2v at r l = 10k ?. electrical specifications t a = 25 o c, v+ = 5v, v- = 0v (continued) parameter symbol test conditions ca5260 CA5260A units min typ max min typ max electrical specifications t a = -55 o c to 125 o c, v+ = 5v, v- = 0v parameter symbol test conditions ca5260 CA5260A units min typ max min typ max input offset voltage v io v o = 2.5v - 3 20 - 2 15 mv input offset current i io v o = 2.5v - 1 10 - 1 10 na input current i i v o = 2.5v - 2 15 - 2 15 na common mode rejection ratio cmrr v cm = 0 to 1v 60 78 - 65 78 - db v cm = 0 to 2.5v 50 60 - 50 60 - db common mode input voltage range v lcr + 2.5 3 - 2.5 3 - v v lcr - - -0.5 0 - -0.5 0 v power supply rejection ratio psrr ? v+ = 1v; ? v- = 1v 60 65 - 62 65 - db large signal voltage gain (note 4) a ol r l = , v o = 0.5 to 4v 70 78 - 70 78 - db r l = 10k ? , v o = 0.5 to 3.6v 60 65 - 60 65 - db source current i source v o = 0v 1.3 1.6 - 1.3 1.6 - ma sink current i sink v o = 5v 1.2 1.4 - 1.2 1.4 - ma output voltage v om + r l = 4.99 5 - 4.99 5 - v v om - - 0 0.01 - 0 0.01 v v om + r l = 10k ? 4.2 4.4 - 4.2 4.4 - v v om - - 0 0.01 - 0 0.01 v v om + r l = 2k ? 2.5 2.7 - 2.5 2.7 - v v om - - 0 0.01 - 0 0.01 v supply current i supply v o = 0v - 1.65 2.2 - 1.65 2.2 ma v o = 2.5v - 1.95 2.35 - 1.95 2.35 ma note: 4. for v+ = 4.5v and v- = gnd; v out = 0.5v to 3.2v at r l = 10k ?. ca5260, CA5260A ca5260, CA5260A
4 electrical specifications each amplifier at t a = 25 o c, v+ = 15v, v- = 0v, unless otherwise specified parameter symbol test conditions ca5260 CA5260A units min typ max min typ max input offset voltage v io v s = 7.5 - 6 15 - 2 5 mv input offset current i io v s = 7.5 - 0.5 30 - 0.5 20 pa input current i i v s = 7.5 - 5 50 - 5 30 pa large signal voltage gain a ol v o = 10v p-p , r l = 10k ? 50 320 - 50 320 - kv/v 94 110 - 94 110 - db common mode rejection ratio cmrr 70 90 - 80 95 - db common mode input voltage range v lcr 10 -0.5 to 12 0 10 -0.5 to 12 0 v power supply rejection ratio, ? v io / ? v psrr v s = 7.5 - 32 320 - 32 150 v/v maximum output voltage v om + r l = 10k ? 11 13.3 - 11 13.3 - v v om - - 0.002 0.01 - 0.002 0.01 v v om + r l = 14.99 15 - 14.99 15 - v v om - - 0 0.01 - 0 0.01 v maximum output current i om + (source) v o = 7.5v 12 22 45 12 22 45 ma i om - (sink) 12 20 45 12 20 45 ma total supply current, r l = i+ v o (amp a) = 7.5v v o (amp b) = 7.5v - 9 16.5 - 9 16.5 ma v o (amp a) = 0v v o (amp b) = 0v - 1.2 4 - 1.2 4 ma v o (amp a) = 0v v o (amp b) = 7.5v - 5 9.5 - 5 9.5 ma input offset voltage temperature drift ? v io / ? t - 8 - - 6 - v/ o c crosstalk f = 1khz - 120 - - 120 - db ca5260, CA5260A ca5260, CA5260A
5 schematic diagram r 6 200k r 7 300k q 12 q 11 q 10 d 2 d 3 d 4 d 1 q 1 q 2 q 6 r 4 1k r 2 1k r 1 1k r 3 1k q 13 q 14 q 3 q 4 c 1 30pf r 5 2k q 7 q 9 3 2 1 q 5 q 8 amplifier a r 13 200k r 14 300 ? q 26 q 25 q 24 d 7 d 6 d 5 d 8 q 15 q 16 q 20 r 11 1k r 9 1k r 8 1k r 10 1k q 27 q 28 q 17 q 18 c 2 30pf r 12 2k q 21 q 23 5 6 7 q 19 q 22 amplifier b 4 8 v+ c 3 c 4 out -in +in v- +in -in ca5260, CA5260A
6 ca5260, CA5260A ca5260, CA5260A small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo seri es symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional . if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millime ter. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 o 8 o 0 o 8 o - rev. 0 12/93
7 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com ca5260, CA5260A dual-in-line plastic packages (pdip) c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a 1 -a- 0.010 (0.25) c a m bs notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protru- sions. mold flash or protrusi ons shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be per- pendicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- e8.3 (jedec ms-001-ba issue d) 8 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.355 0.400 9.01 10.16 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n8 89 rev. 0 12/93
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